Streaming Signal Processors

May 20th, 2004, 08:00 - 09:00, Grand Salon

Presented by

Prof. Bill Dally, Department of EE and CS, Computer Systems Laboratory, Stanford University


Programmable stream processors are capable of efficiency comparable to fixed-function ASIC solutions (about 20pJ/op) and can be scaled from a Gop/s (20mW) to a Top/s (20W) in 0.13um technology. The parallel nature of stream processors enables their performance to scale with technology. In a 2010 45nm technology we expect an efficiency of 1pJ/op and performance of up to 20Top/s (20W). A stream processor contains an array of arithmetic units that are supplied with data by a deep register hierarchy. A compiler automatically maps the signal-flow graph of an application to this array: employing stream scheduling to stage the high-level movement of streams, and communication scheduling to schedule the data movement in the low-level kernels. This explicit optimization of communication results in almost all data and instruction movement taking place over short wires, and hence almost all energy going to useful computation. We have built a prototype streaming signal processor, Imagine, and have demonstrated streaming applications involving video compression/decompression, wireless communication, and adaptive beamforming. This talk will describe stream architectures, stream programming systems, and streaming applications. A comparison will be made to conventional DSPs, FPGAs, and ASIC solutions.

Speaker Biography

Bill Dally received the B.S. degree in Electrical Engineering from Virginia Polytechnic Institute, the M.S. degree in Electrical Engineering from Stanford University, and the Ph.D. degree in Computer Science from Caltech.

Bill and his group have developed system architecture, network architecture, signaling, routing, and synchronization technology that can be found in most large parallel computers today. While at Bell Telephone Laboratories Bill contributed to the design of the BELLMAC32 microprocessor and designed the MARS hardware accelerator. At Caltech he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. While a Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology his group built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanisms from programming models and demonstrated very low overhead synchronization and communication mechanisms. Bill is currently a Professor of Electrical Engineering and Computer Science at Stanford University where his group has developed the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations. Bill has worked with Cray Research and Intel to incorporate many of these innovations in commercial parallel computers, with Avici Systems to incorporate this technology into Internet routers, and co founded Velio Communications to commercialize high-speed signaling technology. He is a Fellow of the IEEE, a Fellow of the ACM and has received numerous honors including the ACM Maurice Wilkes award. He currently leads projects on high-speed signaling, computer architecture, and network architecture. He has published over 150 papers in these areas and is an author of the textbooks, Digital Systems Engineering and Principles and Practices of Interconnection Networks.

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