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| Paper: | DISPS-P2.1 |
| Session: | Fast Algorithms |
| Time: | Friday, May 21, 09:30 - 11:30 |
| Presentation: |
Poster |
| Topic: |
Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware |
| Title: |
HARDWARE ARCHITECTURE AND VLSI IMPLEMENTATION OF A LOW-POWER HIGH-PERFORMANCE POLYPHASE CHANNELIZER WITH APPLICATIONS TO SUBBAND ADAPTIVE FILTERING |
| Authors: |
Yongtao Wang; Purdue University | | |
| | Hamid Madmoodi; Purdue University | | |
| | Lih-Yih Chiou; Purdue University | | |
| | Hunsoo Choo; Purdue University | | |
| | Jongsun Park; Purdue University | | |
| | Woopyo Jeong; Purdue University | | |
| | Kaushik Roy; Purdue University | | |
| Abstract: |
Polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level. At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques. |
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