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| Paper: | DISPS-P1.7 |
| Session: | VLSI Algorithms and Architectures for DSP |
| Time: | Friday, May 21, 09:30 - 11:30 |
| Presentation: |
Poster |
| Topic: |
Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware |
| Title: |
AREA EFFICIENT PARALLEL DECODER ARCHITECTURE FOR LONG BCH CODES |
| Authors: |
Yanni Chen; University of Minnesota | | |
| | Keshab Parhi; University of Minnesota | | |
| Abstract: |
Long BCH codes achieve additional coding gain of around 0.6dB compared to Reed-Solomon codes with similar code rate used for long-haul optical communication systems. For our considered parallel decoder architecture, a novel group matching scheme is proposed to reduce the overall hardware complexity of both Chien search and syndrome generator units by 46$\%$ for BCH(2047, 1926, 23) code as opposed to only 22$\%$ if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs. |
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