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| Paper: | DISPS-L1.5 |
| Session: | VLSI Architectures for Video and Image Processing |
| Time: | Wednesday, May 19, 14:20 - 14:40 |
| Presentation: |
Lecture |
| Topic: |
Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding |
| Title: |
A LOW POWER RECONFIGURABLE DCT ARCHITECTURE TO TRADE OFF IMAGE QUALITY FOR COMPUTATIONAL COMPLEXITY |
| Authors: |
Jongsun Park; Purdue University | | |
| | Kaushik Roy; Purdue University | | |
| Abstract: |
We present a low power reconfigurable DCT design, which achieves considerable computational complexity reduction in DCT operation with minimum image quality degradation. The approach is based on the modification of DCT bases in a bit-wise manner. Different computational complexity/image quality trade off levels are presented and a reconfigurable architecture, which can dynamically change from one trade off level to another, is also proposed. The reconfigurable DCT architecture can achieve power savings ranging from 20% to 70% for 5 different trade off levels. |
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