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| Paper: | DISPS-P1.1 |
| Session: | VLSI Algorithms and Architectures for DSP |
| Time: | Friday, May 21, 09:30 - 11:30 |
| Presentation: |
Poster |
| Topic: |
Design and Implementation of Signal Processing Systems: Algorithm Transformation and Mapping Techniques |
| Title: |
AREA EFFICIENT DECODING OF QUASI-CYCLIC LOW DENSITY PARITY CHECK CODES |
| Authors: |
Zhongfeng Wang; Oregon State University | | |
| | Yanni Chen; University of Minnesota | | |
| | Keshab Parhi; University of Minnesota | | |
| Abstract: |
This paper exploits the similarity between the two stages of belief propagation decoding algorithm for low density parity check codes to derive an area efficient design that re-maps the check node functional units and variable node functional units into the same hardware. Consequently, the novel approach could reduce the logic core size by approximately 21$\%$ without any performance degradation. In addition, the proposed approach improves the hardware utilization efficiency as well. |
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