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| Paper: | DISPS-L1.6 |
| Session: | VLSI Architectures for Video and Image Processing |
| Time: | Wednesday, May 19, 14:40 - 15:00 |
| Presentation: |
Lecture |
| Topic: |
Design and Implementation of Signal Processing Systems: Algorithm Transformation and Mapping Techniques |
| Title: |
PIPELINING OF PARALLEL MULTIPLEXER LOOPS AND DECISION FEEDBACK EQUALIZERS |
| Authors: |
Keshab Parhi; University of Minnesota | | |
| Abstract: |
High speed implementation of a DFE (decision feedback equalizer )requires reformulation of the DFE into an array of comparators and a multiplexer loop. The throughput of the DFE is limitedby the speed of the multiplexer loop. This paper proposes a novel look-ahead computation approach to pipeline multiplexer loops. The proposed technique is demonstrated and applied to design multiplexer loop based DFEs with throughput in the range of 3.125 - 10 Gbps. |
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