Technical Program

Paper Detail

Paper:DISPS-P4.5
Session:Design and Mapping Techniques
Time:Friday, May 21, 13:00 - 15:00
Presentation: Poster
Topic: Design and Implementation of Signal Processing Systems: Hardware, Software, and Algorithm Tradeoffs and Integration
Title: REDUCED FLOATING POINT FOR MPEG1/2 LAYER III DECODING
Authors: Mikael Olausson; Linköping University 
 Andreas Ehliar; Linköping University 
 Johan Eilert; Linköping University 
 Dake Liu; Linköping University 
Abstract: A new approach to decode MPEG1/2-Layer III, mp3, is presented. Instead of converting the algorithm to fixed point we propose a 16-bit floating point implementation. These 16 bits include 1 sign bit and 15 bits of both mantissa and exponent. The dynamic range is increased by using this 16-bit floating point as compared to both 24 and 32-bit fixed point. The 16-bit floating point is also suitable for fast prototyping. Usually new algorithms are developed in 64-bit floating point. Instead of using scaling and double precision as in fixed point implementation we can use this 16-bit floating point easily. In addition this format works well even for memory compiling. The intention of this approach is a fast, simple, low power, and low silicon area implementation for consumer products like cellular phones and PDAs. Both listening tests and tests versus the psychoacoustic model has been completed.
 
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