Technical Program

Paper Detail

Paper:ITT-P2.10
Session:Communication Technoloiges
Time:Friday, May 21, 09:30 - 11:30
Presentation: Poster
Topic: Industry Technology Track: DSP Chips and Architectures
Title: CACHED MEMORY PERFORMANCE CHARACTERIZATION OF A WIRELESS DIGITAL BASEBAND PROCESSOR
Authors: Srikanth Kannan; Analog Devices 
 Michael Allen; Analog Devices 
 Jose Fridman; Analog Devices 
Abstract: In this paper we present performance analysis results of the MSP500 Digital Baseband (DBB) platform, a system developed at Analog Devices, Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which integrates a Blackfin® core, and examine the execution time performance of a number of wireless physical layer software components from the perspective of an instruction- and data-cached memory hierarchy. The Blackfin is a 16-bit fixed-point core that combines some of the best features of DSPs and micro-controllers, and has support for a cached memory system
 
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