| Paper: | DISPS-P3.1 | ||
| Session: | High Performance DSP Architectures and Systems | ||
| Time: | Friday, May 21, 13:00 - 15:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | A DATA MERGING TECHNIQUE FOR HIGH-SPEED LOW-POWER MULTIPLY ACCUMULATE UNITS | ||
| Authors: | Ayman Fayed; Intel Corporation | ||
| Walid Elgharbawy; University of Louisiana at Lafayette | |||
| Magdy Bayoumi; University of Louisiana at Lafayette | |||
| Abstract: | In an attempt to meet the low-power requirements of high performance portable signal processing VLSI systems, while maintaining a high operating speed, a new data merging architecture for high speed multiply accumulate units is proposed. The architecture can be applied on binary trees constructed using 4:2 compressor circuits. Increasing the speed of operation is achieved by taking advantage of the available free input lines of the compressor circuits, which result from the natural parallelogram shape of the generated partial products and using the bits of the accumulated value to fill in these gaps. This results in merging the accumulation operation within the multiplication process. | ||
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