Technical Program

Paper Detail

Paper:DISPS-P3.5
Session:High Performance DSP Architectures and Systems
Time:Friday, May 21, 13:00 - 15:00
Presentation: Poster
Topic: Design and Implementation of Signal Processing Systems: Design Methodology and Rapid Prototyping
Title: A NOVEL HIGH PERFORMANCE DISTRIBUTED ARITHMETIC ADAPTIVE FILTER IMPLEMENTATION ON AN FPGA
Authors: Daniel Allred; Georgia Institute of Technology 
 Heejong Yoo; Georgia Institute of Technology 
 Venkatesh Krishnan; Georgia Institute of Technology 
 Walter Huang; Georgia Institute of Technology 
 David Anderson; Georgia Institute of Technology 
Abstract: In this paper, a FIR adaptive filter implementation using a multiplier free architecture is presented. The implementation is based on Distributed Arithmetic that substitutes multiply and accumulate operations with a series of look-up-table accesses. The proposed design performs an LMS type adaptation on a sample-by-sample basis. This is achieved by an innovative LUT update using a matched auxiliary LUT. The system is implemented on a FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high- speed, low logic complexity LMS adaptive filter can be realized employing the proposed architecture. This can achieved at the cost of a moderate increase in memory usage.
 
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