| Paper: | DISPS-P1.10 | ||
| Session: | VLSI Algorithms and Architectures for DSP | ||
| Time: | Friday, May 21, 09:30 - 11:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding | ||
| Title: | BIT-PLANE AND PASS DUAL PARALLEL ARCHITECTURE FOR COEFFICIENT BIT MODELING IN JPEG2000 | ||
| Authors: | Chao Xu; Peking University | ||
| Yanju Han; Peking University | |||
| Yizhen Zhang; Peking University | |||
| Abstract: | In this paper, the bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000 is proposed. It is a very high speed and efficient structure that is capable of encoding all bits of the wavelet coefficient in only one scan, and largely decreases the memory requirement. Additionally in order to decrease the logic circuit requirement we propose a partial parallel technique to replace the whole channel parallelism. Experimental results show that the architecture can encode at a speed about 15 times the existing parallel encoding for the coefficient with 16 bits, and it only requires 2K bits memory instead of 16K bits for the pass parallel encoding or 60K bits for the subband parallel encoding. | ||
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