Technical Program

Paper Detail

Paper:DISPS-P4.9
Session:Design and Mapping Techniques
Time:Friday, May 21, 13:00 - 15:00
Presentation: Poster
Topic: Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware
Title: A THINNING PROCESS FOR AN IMPLEMENTATION IN A PIXEL ARRAY CIRCUIT
Authors: Kuo-Ting Wu; Concordia University 
 Chunyan Wang; Concordia University 
Abstract: In this paper, a thinning process suitable for pixel array circuit implementation is presented. The process is designed to have the computations in parallel and to include only simple logic operations so that the structure of each pixel will be simple and the array circuit will have an acceptable resolution. Simulation with images of different patterns, including fingerprints, demonstrated that the proposed thinning process is efficient, and its results meet the requirement of the minutia detection for identification. The structure of such a pixel array circuit is also designed as an example of implementation and presented in the paper. The circuit has four interconnections per pixel, and can be implemented in a digital CMOS process.
 
           Back


Home -||- Organizing Committee -||- Technical Committee -||- Technical Program -||- Plenaries
Paper Submission -||- Special Sessions -||- ITT -||- Paper Review -||- Exhibits -||- Tutorials
Information -||- Registration -||- Travel Insurance -||- Housing -||- Workshops

©2015 Conference Management Services, Inc. -||- email: webmaster@icassp2004.org -||- Last updated Wednesday, April 07, 2004