Technical Program

Paper Detail

Paper:SPCOM-P4.10
Session:Iterative Decoding Algorithms and Architectures
Time:Wednesday, May 19, 09:30 - 11:30
Presentation: Poster
Topic: Signal Processing for Communications: Compression, Coding, and Modulation
Title: JOINT GRAPH-DECODER DESIGN OF IRA CODES ON SCALABLE ARCHITECTURES
Authors: Frank Kienle; University of Kaiserslautern 
 Norbert Wehn; University of Kaiserslautern 
Abstract: Channel coding is an important building block in communicationsystems since it ensures the quality of service.Irregular repeat-accumulate (IRA) codes belong to the class of Low-Density Parity-Ceck (LDPC) codes and even outperform the recently introduced Turbo-Codes of current communication standards. The advantage of IRA codes over LDPC codes is that they come with a linear-time encoding complexity.IRA codes can be represented by a Tanner graph with arbitraryconnections between nodes of given degrees. The implementation complexity of an IRA decoders is dominated by the randomness of these connections.In this paper we present a scalable partly parallel IRA decoderarchitecture. We present a joint graph-decoder design to parallalize IRA codes which can be efficiently processed by this decoder without any RAM access conflicts.We show design examples of these IRA codes which outperform the UMTS Turbo-Code by 0.2dB.
 
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